1. Field of the Invention
This invention relates to semiconductor fabrication, and more particularly to a method for fabricating a stack capacitor with a hemi-spherical grain (HSG) structure.
2. Description of Related Art
A semiconductor memory, such as a dynamic random access memory (DRAM), typically includes a transistor and a capacitor. Quality of a memory does strongly depend on performance of both the transistor and the capacitor. Intentions to improve the semiconductor memory are concentrated on how to improve abilities of the transistor and the capacitor.
As semiconductor fabrication technology achieves a deep sub-micron level, device dimension is greatly reduced. For a memory structure, as the structure dimension is reduced, it means that the capacitor dimension is also reduced, causing a smaller capacitance. On the other hand, since the computer application software size also increases a lot, it needs to be supported by a large number of memory cells. It becomes a trend to reduce the memory dimension to satisfy the need of software. In this situation, it is a challenge to fabricate a greatly reduced memory dimension with sufficient capacitance.
Currently, there are two main considering points to improve capacitance with reduced dimension. One is using a dielectric material with high dielectric constant K, and the other one is increasing the capacitor surface. The dielectric material with high dielectric constant includes, for example, tantalum oxide (Ta.sub.2 O.sub.5) with K about equal to 25 or Barium titanate (BaTiO.sub.3) with K even as high as about 1000.
About the solution of increasing the capacitor surface, there are also two main methods. One is called a deep-trench type and the other one is called a stack type. The deep-trench capacitor typically includes a trench with a depth of about 6-7 microns. After filling the deep trench with a dielectric material, a deep-trench capacitor is formed. The deep-trench capacitor can have a large capacitance but it is difficult to be formed. The deep-trench capacitor may be a main trend in the future but not now.
The stack-type capacitor is the main type for the current fabrication trend. Since the stack-type capacitor still has its advantages, semiconductor manufacturers, such as NEC company in Japan or Sumsung company in Korea, have made a lot of efforts to develop a memory device with few mega bits of memory cells at a fabrication level less than 0.25 microns. In this manner, the HSG technology is one of the main technologies being used.
FIGS. 1A-1C are cross-sectional views, schematically illustrating a conventional fabrication process to form a stack capacitor.
In FIG. 1A, an amorphous silicon layer 102 formed over a substrate 100. The substrate 100 includes a semiconductor substrate 101, an oxide layer 104 on the semiconductor substrate 101, and a conductive plug 104 in the substrate 100 serving as a lower electrode of a capacitor. The conductive plug 104, for example, is a Si plug 104.
The amorphous silicon layer 102 is formed by low pressure chemical vapor deposition (LPCVD) at a temperature of 520.degree. C. for 13 hours so as to obtain a thickness of 6000 angstroms. During the formation of the amorphous silicon layer 102, phosphorous ions are in-situ doped. The dopant concentration is about 2.times.10.sup.20 atoms/cm.sup.3.
In FIG. 1B, the amorphous silicon layer 102 is patterned to form a storage node 102a, which is a remaining portion of the amorphous silicon layer 102 covering the Si plug 14. A HSG layer 108 is formed over an exposed surface of the storage node 102a. The formation of the HSG layer 108 includes performing a seeding process at an ultra high vacuum environment with silane (SiH.sub.4) gas. A large number of HSG crystal nuclei are formed on the exposed surface of the storage node 102a. Then, still at the high vacuum environment, a thermal process is performed so as to allow the silicon atoms of the storage node 102a to be migrated to the HSG nuclei. As a result, the HSG layer 108 is formed on the exposed surface of the storage node 102a. The HSG layer produces more charge storage surface.
In FIG. 1C, a capacitor dielectric layer 110 conformal to the surface of the storage node 102a and the HSG layer 108 is formed by LPCVD. The capacitor dielectric layer 110 includes silicon oxide or a structure of silicon-oxide/silicon-nitride/silicon-oxide (O/N/O). A conductive layer 112 serving as an upper electrode of the capacitor is formed to cover the capacitor dielectric layer 110.
In this conventional method, it take long to form the amorphous silicon layer 102. The throughput is strongly affected. The amorphous silicon layer 102 may also be easily converted to a polysilicon structure, causing difficulty to form the HSG layer 108.
Moreover, since the dopant concentration in the amorphous silicon layer 102 is not sufficiently large, an undoped silicon film may often form on the surface of the HSG layer 108 while the HSG layer is formed. The undoped silicon film causes a capacitance depletion effect. Usually, the capacitance is degraded by about 15% if the undoped silicon film occurs.
Even though the capacitance depletion effect can be reduced by increasing the dopant concentration in the storage node 108, the silicon atom migration performance is degraded. It becomes more difficult to form the HSG layer.